Generally, integrated circuits (ICs) comprise individual devices, such as transistors, capacitors, or the like, formed on a substrate. One or more metal layers are then formed over the individual devices to provide connections between the individual devices and to provide connections to external devices. The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) are patterned in a wafer. FEOL generally covers everything up to (but not including) the deposition of metal layers. The back end of line (BEOL) is the second portion of IC fabrication where the individual devices get interconnected with wiring or metal layers on the wafer. BEOL generally begins when the first metal layer is deposited on the wafer. It includes contacts, insulating layers, metal layers, and bonding sites for chip-to-package connections.
The metal layers interconnecting individual devices typically comprise an inter-metal dielectric (IMD) layer in which interconnect structures, such as vias and conductive lines, are formed, through numerous and repetitive steps of deposition, patterning and etching of thin films on the surface of silicon wafer. While aluminum and aluminum alloys were most frequently used in the past for the metal layers, the current trend is to use copper (Cu) for metal layers because copper has better electrical characteristics than aluminum, such as decreased resistance, higher conductivity, and a higher melting point.
Barrier layers are used to prevent diffusion of the conductor materials of the metal layers, such as the aluminum or Cu, into the adjacent areas of the IC. As the interconnect line widths shrink continuously, how to fabricate the barrier layers with ultra thin, conformal coatings and excellent conductivities is an important issue to resolve and needs new methods and apparatus.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.